PBT8869A Series 800G Error Detector
The PBT8869A Series 800G Error Detector is a reliable and high-performance device designed for testing PAM4 and NRZ signal generation and error detection. It supports high-speed data rates and provides comprehensive error analysis capabilities.
Specification Snapshot
Power Consumption
≤23W
Maximum Differential Input Voltage
1.0V
JTOL Test Bandwidth
30MHz
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Overview
The PBT8869A Series 800G Error Detector is a reliable and high-performance device designed for testing PAM4 and NRZ signal generation and error detection. It supports high-speed data rates and provides comprehensive error analysis capabilities.
Specifications
| Parameter | Value |
|---|---|
| Device Dimensions | 320mm(length)×335mm(width)×95mm(height) |
| Communication Interface | LAN port |
| Power Supply Voltage | 220VAC |
| Power Consumption | ≤23W |
| Weight | ≤4kg |
| Storage Temperature | -20°C-80°C |
| Operating Humidity | 35°C, 20%-80% |
| Output Interface | 2.4mm female |
| Standard Channel Output Clock Frequency | 8.5GHz-28GHz |
| Output NRZ Rate | 25.78125/26.5625/51.5625/53.125Gbps |
| Output PAM4 Rate | 25.78125/26.5625/51.5625/53.125Gbaud |
| Reference Clock Input | 50MHz-400MHz, amplitude 600mV±200mV @50Ω |
| Random Jitter RJ | ≤10mUI RMS, ≤300fs@28Gbps |
| Total Jitter Tj | ≤0.25UI |
| Duty Cycle Distortion DCD | ≤0.035UI |
| Deterministic Jitter Dj | ≤0.15UI |
| Rise/Fall Time | 15ps(typ) |
| Single-ended Output | 20mV-500mV/1000mV |
| Differential Output | 40mV-1000mV/2000mV |
| Polarity Inversion | Supported |
| Post-cursor1 | 0-6dB |
| Post-cursor2 | 0-6dB |
| Pre-cursor1 | 0-6dB |
| Output Impedance | 100ohm |
| Clock Model | CLK, CLK_DIV2, CLK_DIV4, CLK_DIV8, CLKDIV_16, CLKDIV_32 |
| Supported Patterns | PRBS7/9/11/13/15/16/23/31/58, PRBS13Q, SSPRQ, 128bit user-defined |
| Maximum Differential Input Voltage | 1.0V |
| Input Sensitivity | 40mV |
| Input Impedance | 50ohm |
| CDR Clock Recovery Output | 8.5GHz-28GHz |
| CDR Data Recovery Output | 32Gbps full rate |
| Clock Recovery Module Differential Data Input Interface | 2.92mm Female |
| Clock Recovery Module Differential Data and Clock Input Interface | 2.92mm Female |
| PAM4 Decoding | Supports 1 PAM4 decoding channel to 2 NRZ outputs |
| Input Data Rate | 25.78125/26.5625/51.5625/53.125Gbps NRZ, 25.78125/26.5625/51.5625/53.125Gbaud PAM4 |
| Built-in Equalizer | Automatic equalizer or manual equalizer |
| Recovered Output Clock Frequency | 8.5GHz-28GHz |
| Input Signal Voltage Sensitivity | 25mV |
| JTOL Test Bandwidth | 30MHz |
| BER Test Function | Supported |
| BER Multiplication | Supported |
| RLM | 0.95-0.994 |
Applications
1. High-speed data communication testing 2. Signal generation and error detection for PAM4 and NRZ formats 3. Transmitter linearity testing
Key Features
1. Supports independent 8-channel signal generation and error detection 2. Compatible with PAM4 and NRZ formats 3. High-speed data rates up to 800G 4. Comprehensive error analysis capabilities 5. Built-in equalizer and clock recovery module
Datasheet
Product Datasheet
PDF
Supplier Information
<p>Shanghai Steligent Information Technologies Co., Ltd. was founded in 2015 and focuses on the research and development of high-speed communication test equipment and 100G/400G/800G ultra-high-speed optical communication modules. Test equipment and test systems are the core products, forming a series of products and targeted solutions for scientific research institutes, enterprises, testing and other industries, different scales, and different applications. It is the most influential equipment and technology provider of high-speed communication test equipment solutions and high-speed optical communication modules in China.</p>
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