NIS-L512-125 (CIS)
NIS-L512-125 is a compact 512-pixel linear image sensor designed specifically for image-input applications.
Specification Snapshot
Pixel Count
512
Pixel Height
250 μm
Pixel Pitch
12.5 μm
Supply Voltage Vdd [Maximum Ratings;Ta=25°C]
min:-0.3 V; max:6 V
Operating Temperature Topr [Maximum Ratings;Ta=25°C]
min:-40 °C; max:85 °C
Storage Temperature Tstg [Maximum Ratings;Ta=25°C]
min:-40 °C; max:85 °C
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Overview
NIS-L512-125 is a compact 512-pixel linear image sensor designed specifically for image-input applications.
Specifications
| Parameter | Value |
|---|---|
| Pixel Count | 512 |
| Pixel Height | 250 μm |
| Pixel Pitch | 12.5 μm |
| Supply Voltage Vdd [Maximum Ratings;Ta=25°C] | min:-0.3 V; max:6 V |
| Clock Pulse Voltage V(CLK) [Maximum Ratings;Ta=25°C] | min:-0.3 V; max:6 V |
| Startup Pulse Voltage V(ST) [Maximum Ratings;Ta=25°C] | min:-0.3 V; max:6 V |
| Operating Temperature Topr [Maximum Ratings;Ta=25°C] | min:-40 °C; max:85 °C |
| Storage Temperature Tstg [Maximum Ratings;Ta=25°C] | min:-40 °C; max:85 °C |
| Peak Reflow Soldering Temperature Tsol [Maximum Ratings;Ta=25°C] | max:260(3 times) |
| Supply Voltage Vdd [Recommended Terminal Voltage;Ta=25°C] | min:4.75 V; typical:5 V; max:5.25 V |
| Clock Pulse Voltage V(CLK) [Recommended Terminal Voltage;Ta=25°C;High Level] | min:Vdd-0.25; typical:Vdd; max:Vdd+0.25 |
| Startup Pulse Voltage V(ST) [Recommended Terminal Voltage;Ta=25°C;High Level] | min:Vdd-0.25; typical:Vdd; max:Vdd+0.25 |
| Clock Pulse Frequency f(CLK) [Ta=25°C;Vdd=5V;V(CLK)=V(ST)=5V;unless otherwise stated] | min:50k; max:5M |
| Data Rate DR [Ta=25°C;Vdd=5V;V(CLK)=V(ST)=5V;unless otherwise stated] | typical:f(CLK) |
| Current Consumption Ic [Ta=25°C;Vdd=5V;V(CLK)=V(ST)=5V;unless otherwise stated;f(CLK)=5MHz] | typical:20 mA |
| Spectral Response Range λ [Ta=25°C;Vdd=5V;V(CLK)=V(ST)=5V;unless otherwise stated;f(CLK)=5MHz] | min:400 nm; max:1000 nm |
| Peak Response Wavelength λp [Ta=25°C;Vdd=5V;V(CLK)=V(ST)=5V;unless otherwise stated;f(CLK)=5MHz] | typical:700 nm |
| Dark Output Voltage VD [Ta=25°C;Vdd=5V;V(CLK)=V(ST)=5V;unless otherwise stated;f(CLK)=5MHz;Integration time=10ms] | typical:1 mV; max:10 mV |
| Saturated Output Voltage Vsat [Ta=25°C;Vdd=5V;V(CLK)=V(ST)=5V;unless otherwise stated;f(CLK)=5MHz;Voltage difference from Voffset] | typical:4.2 V |
| Readout Noise Nread [Ta=25°C;Vdd=5V;V(CLK)=V(ST)=5V;unless otherwise stated;f(CLK)=5MHz] | typical:0.6 mV rms |
| Output Offset Voltage Voffset [Ta=25°C;Vdd=5V;V(CLK)=V(ST)=5V;unless otherwise stated;f(CLK)=5MHz] | typical:0.7 V |
| Startup Pulse Interval tpi(ST) [Timing Characteristics; Values from an Independent Table, Not a Waveform Plot] | Min:530/f(CLK) s;Max:1100 m s |
| Start Pulse High-Level Duration thp(ST) [Timing Characteristics; Values from an Independent Table, Not a Waveform Plot] | Min:8/f(CLK) s;Max:1000 m s |
| Start Pulse Low-Level Duration tlp(ST) [Timing Characteristics; Values from an Independent Table, Not a Waveform Plot] | Min:15/f(CLK) s;Max:100 m s |
| Start Pulse Rise and Fall Time tr(ST), tf(ST) [Timing Characteristics; Values from an Independent Table, Not a Waveform Plot] | min:0 ns; typical:20 ns; max:30 ns |
| Clock Pulse Duty Cycle [Timing Characteristics; Values from an Independent Table, Not a Waveform Plot] | min:45 %; typical:50 %; max:55 % |
| Clock Pulse Rise and Fall Time tr(CLK), tf(CLK) [Timing Characteristics; Values from an Independent Table, Not a Waveform Plot] | min:0 ns; typical:20 ns; max:30 ns |
| Video Signal Delay Time 1 tvd1 [Timing Characteristics; Values from an Independent Table, Not a Waveform Plot] | typical:40 ns |
| Video Signal Delay Time 2 tvd2 [Timing Characteristics; Values from an Independent Table, Not a Waveform Plot] | typical:50 ns |
| Integration Time [Independent Note below Timing Table] | ST pulse high period + 6 CLK cycles |
| First Pixel Output Time [Independent Note below Timing Table] | 14 clocks plus 100ns after falling edge of ST pulse |
| EOS Pulse Output Time [Independent Note below Timing Table] | 39ns after falling edge of CLK pulse |
Applications
Position Detection; Image Reading
Key Features
Built-In Timing Generator Needs Only Start/Clock;Global Shutter;Pixel Height250μm/Pitch12.5μm;PIN5 Video Output Requires Buffer Impedance Conversion to Reduce Current,Recommended High-Input-Impedance JFET/CMOS-Input Op-Amp;Dark Output Increases with Longer Start Period/High Time;Internal Timing Starts at First CLK Rise after ST Goes Low;Output after Last512th Pixel Is Indefinite;Example Minimum Start Period/Maximum Integration:Start High=515/f(CLK),Low=15/f(CLK);Remove Photosensitive-Area Protective Tape after Assembly/before Use
Datasheet
Product Datasheet
PDF
Supplier Information
Shanghai Enbi Technology Co., Ltd., founded in 2016, focuses on optoelectronic technology R&D and production. Based on optoelectronic semiconductor discrete devices, it integrates optics, MEMS, electronics, microelectronics, semiconductor optoelectronic IC technologies, covering components, optoelectronic ICs, sensor modules, with full capability from chip design to module mass production, holding independent IP and unique testing systems. The company has an excellent management team and skilled staff, rich industry experience, strong R&D, efficient mass production and strict quality control, providing high-performance, reliable, cost-effective products; for special applications, we offer optimal optoelectronic solutions and custom products. Since its establishment, the company insists on independent innovation, quality first, continuously launching innovative products widely used in industrial equipment, automotive electronics, laser ranging, healthcare, instrumentation, security monitoring, smart home, etc., with performance replacing high-end foreign brands. Enbi Technology actively deploys in IoT, intelligent society, AI, driving industry upgrades, aiming to become a high-end optoelectronic brand.
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