ALP-4 Controller Kits

ALP-4 controller suites provide a general platform for advanced DLP micromirror control, with extensive libraries for industrial,medical,research and development applications. The first ALP Controller SuiteTM accompanied TI's first DLP Discovery chipset in 2001. FPGA-based chipsets have been supported for years with full API compatibility. ALP-4 lets customers begin designs without lengthy software,firmware or high-frequency FPGA development. Control/dataflow are shown in the left diagram: unlike multimedia projection,patterns are generated on PC and uploaded through compressed USB to onboard memory; sophisticated FPGA logic processes/streams them to the array. ALP-4 is included in all V-modules,as shown right,and is an accessory for TI DLP Discovery4100 EVM. ALP-4 API is proven from concepts to development/series production. Portable DLL supports C++,C#,Visual Basic(.NET),Python,MATLAB,LabVIEW and others; Python runs on Microsoft Windows. ALP-4.3 uses USB 3.0 SuperSpeed and lossless compression for higher effective transfer,with low-latency array updates for PC feedback at cycles ≤1.5ms. ALP-4.3 flexibility supports diverse uses; custom ALP-4.3 sequences and four operation modes are available. Binary sequences are defined in the application/uploaded to RAM,with exact display timing. ALP-4 spans picture times from 20µs to seconds,allowing stationary mirrors or switching to 50kHz. Comprehensive triggering synchronizes external equipment in master/slave modes. Queued sequences upload/display in parallel and link without gaps. DMD shows only binary patterns at any instant; grayscale requires timed multiple binary frames. ALP-4 generates gray values with FPGA precision. Maximum 'drill depth',as worded in the source,is 12 bits,with lower resolution selectable. Synchronized detectors provide 10ppm grayscale linearity for DLP metrology. Grayscale sequences contain specified bitplanes; ALP-4 PWM generates 260-300fps on different chipsets at 8 bits. Triggering affects the whole grayscale image for easy camera synchronization. Flex PWM allows external-trigger control of bitplane timing. ALP-4 supports indirect selection through frame lookup tables FLUT. Sequences use RAM patterns pointed to by FLUT entries,allowing flexible generation/modification merely by changing tables. Repeating patterns without storing copies saves upload time/memory; one use is delta-sigma grayscale coding. Moving DLP exposure heads serve lithography and 3D printing. Patterns slide across arrays at the same speed by uploading strips to RAM and traversing line by line,adding one line and dropping another each step,substantially reducing PC uploads. Rotating sliding patterns use additional on-the-fly shearing. Permanent pixel masks modify final target exposure.

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